XC2S50-5TQG144C

Programmable Gate Array, mask-programmed ASICs, no hardware replacement necessary

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Price:: US $4.00~7.00 / piece [Get Latest Price]

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PartNumber:: XC2S50-5TQG144C

Brand:: Xilinx, Inc - Xilinx | Pack: TQFP | D/C: 09+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-04-05

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Part Number:XC2S50-5TQG144C
US $4.00 - 7.00
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Product Summary

The XC2S50-5TQG144C is a member of the Spartan-II Field-Programmable Gate Array family, which gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates. The Spartan-II family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Parametrics

Absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND:–0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input reference voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND: 5V tolerant I/O:–0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (5)VTS, Voltage applied to 3-state output: 5V tolerant I/O: –0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (6)TSTG, Storage temperature (ambient): –65 to +150 ℃ ; (7)TJ, Junction temperature: +125 ℃ max.

Features

Features: (1)Second generation ASIC replacement technology: Densities as high as 5,292 logic cells with up to 200,000 system gates; Streamlined features based on Virtex FPGA architecture; Unlimited reprogrammability; Very low cost; Cost-effective 0.18 micron process; (2)System level features:Select RAM hierarchical memory:16 bits/LUT distributed RAM; Configurable 4K bit block RAM; fast interfaces to external RAM; Fully PCI compliant; Low-power segmented routing architecture; Full readback ability for verification/observability; Dedicated carry logic for high-speed arithmetic; Efficient multiplier support; Cascade chain for wide-input functions; (3)Versatile I/O and packaging; (4)Core logic powered at 2.5V and I/Os powered at 1.5V, 2.5V, or 3.3V; (5)Fully supported by powerful Xilinx ISE development system.